FIGS. 1a, 1b show sampling signal amplifiers according to the prior art, with FIG. 1a showing a simple embodiment and FIG. 1b showing a differential embodiment. The sampling signal amplifiers are used for sampling and amplification of an analogue input signal which is applied to a signal input E, with the amplified signal being emitted via a signal output A. For this purpose, the sampling signal amplifier according to the prior art, and as is illustrated in FIGS. 1a, 1b, contains a sampling capacitor CA and an inverting amplifier, whose output is fed back via a control switch to the input. The control switch is driven by a sampling control signal.
FIG. 2 shows a further sampling differential amplifier according to the prior art, which has particularly simple circuitry. The sampling differential amplifier is in a differential form and contains signal amplification transistors N1, N1 which, in the embodiment illustrated in FIG. 2, are in the form of NMOS field-effect transistors. Sampling capacitors CA, CA are connected to the gate connections of the signal amplification transistors, and are connected to a signal input E. The input signal to be amplified is applied to the signal input E. The source connections of the signal amplification transistors N1, N1 are connected via an NMOS transistor N3 to a negative supply voltage Vss with the NMOS transistor N3 forming a current source. For this purpose, a bias voltage is applied to the gate connection of the transistor N3. The drain connections of the signal amplification transistors N1, N1 are connected via load resistances RL and RL to a positive supply voltage VDD. Furthermore, the signal output A of the sampling differential amplifier is tapped off the drain connections of the NMOS field-effect transistors N1, N1.
The sampling differential amplifier according to the prior art, as it is illustrated in FIG. 2, also contains sampling switching transistors N2, N2, which likewise are NMOS transistors. The gate connections of the NMOS transistors N2, N2 are connected to a control input, to which a sampling control signal is applied. The sampling control signal is a periodic signal, with the two sampling switching transistors N2, N2 being switched on in the first clock phase or sampling phase. This sampling phase is also referred to as the compensation phase or auto-zero phase, since the applied input voltage is at the same time stored with the offset-voltage of the amplifier stage by the sampling capacitors CA, CA. In a second clock phase, the sampling switching transistors N2, N2 are opened, so that the sampling amplifier reacts sensitively to changes in the input voltage.
The gain of the sampling signal amplifier, as it is illustrated in FIG. 2, that is to say the ratio of the output voltage Vout to the input voltage Vin, depends on the gradient of the signal amplification transistors N1, N1 and the voltage drop across the load resistances RL, RL.
Thus:
                    K        =                                            V              out                                      V              in                                ≈                      RL            ·            gm                                              (        1        )            The signal gain K is thus directly proportional to the voltage drop across the load resistance RL.
The disadvantage of the sampling differential amplifier according to the prior art, as it is illustrated in FIG. 2, is that the sampling differential amplifier cannot produce any significant signal gains at very low supply voltages VDD-Vss of, for example, less than 1 volt. This is because, if the supply voltage VDD-Vss falls, the voltage drop across the load resistance RL decreases, and the signal gain likewise decreases.
A sampling differential amplifier with the circuitry shown in FIG. 3 has thus been proposed. In the sampling differential amplifier according to the prior art as illustrated in FIG. 3, current sources are connected in parallel with the load resistances RL, RL. The current sources are formed by field-effect transistors to whose gate connections a bias voltage is applied. As the bias voltage Vbias1 increases, the current ISQ in each case produced by a current source increases, so that if the current IN1 which is flowing through the signal amplification transistor N1 is constant, the current IRL flowing through the load resistance RL decreases. It is thus possible to increase the load resistance RL so that the signal gain K of the sampling differential amplifier is increased.
However, the sampling differential amplifier according to the prior art as illustrated in FIG. 3 likewise has a number of significant disadvantages. The circuitry complexity is increased by the current sources which must additionally be provided. Furthermore, the parasitic capacitances increase. In addition, a mismatch can occur between the current sources (which are connected in parallel with the load resistances) and the current source N3, so that it is necessary to provide a common-mode feedback circuit.